About Me
I’m Rahul, a Hardware Security enthusiast. I work as a Full-Chip Security Validation Engineer at AMD, where I work on validating security features in next-generation EPYC server platforms. I am particularly involved in improving security validation methodologies, identifying coverage gaps in existing validation flows, developing automated test frameworks, and analyzing validation results to detect and triage hardware security issues. I work on validating SoC-level security mechanisms such as secure boot and attestation.
Previously, I completed my PhD in Computer Engineering at Texas A&M University, where my research focused on advancing hardware security verification through automated vulnerability detection techniques such as hardware fuzzing and AI-assisted verification. My work led to multiple publications in top-tier venues including USENIX Security, IEEE TIFS, DAC, and DATE, and has been recognized through industry collaborations, invited talks, and research awards. I was also one of the organizers of the Hack@EVENT hardware security competitions (including Hack@DAC), These competitions have engaged over 1,500 participants from 30+ countries across academia and industry, and several vulnerability benchmarks developed through this effort are now referenced in MITRE’s CWE database.
During my internship at Intel as an Offensive Security Researcher, I contributed to the development of automated static analysis techniques for verifying security-critical RTL logic in processor designs.
My broader interests include hardware security, processor and SoC validation, hardware fuzzing, AI-assisted verification, and secure hardware design.
Research Interests Link to heading
- Hardware Fuzzing
- Hardware Vulnerability Detection
- Secure Computer Architecture
Education Link to heading
Ph.D. in Computer Engineering, July 2018 - May 2026
Texas A&M University, College Station, Texas
Bachelor of Technology in Electronics and Communication Engineering, May 2013 – May 2017
Indian Institute of Technology, Guwahati, India